Economical 1000-core processor

Kilo core chip of the University of California, Davis

Kilo core chip of the University of California, Davis

(Image: University of California, Davis)

Researchers at the University of California have developed a chip that combines 1,000 tiny 16-bit cores, which can be programmed independently.

For years working Professor Bevan Baas from the University of California at Davis to many-core processors; In 2006 he had introduced the 36-polycyclic ASAP, ASAP later the two with 167 cores. Now one of its VLSI Computation Lab team has presented the kilo Core: a chip with 1,000 independently programmable cores. It is about Multiple Instructions, Multiple Data (MIMD).

The Kilo Core is not only the chip with the most cores, but also the chip with the highest CPU clock frequency that has ever been developed by a University: Up to 1.87 GHz cores create stable they ran at 1.78 GHz. Then all the arithmetic units together provide 1.78 trillion operations per second. but this is not about consuming floating point operations, so flops, but simpler instructions, of which the Kilo Core mastered 72 different.

Economically and efficiently

Kilo Core core and on-chip memory A Packet Switched Network, a Circuit Switched Network link 1000 cores 12 and memory areas of the Kilo Core with each other.(Image: University of California, Davis)

At low clock frequency of the core kilos thanks to low operating voltage very efficient: At 115 MHz, it processed 115 billion operations per second and then takes only 1.3 watts of power. For 1GHz he needs 0.84 volts and then needed just 13.1 watts, as declared at the 2016 Symposium on VLSI Technology and Circuits presented paper.

manufactures the chip "IBM" - rather well Globalfoundries - with 32-nm Structures in PD-SOI technology. Two on-chip networks connect 1000 cores with 12 independent memory blocks each including 64 Kbytes of SRAM. In each core a separate router circuit infected with its own clock. Overall, the chip has oscillators 2012 (1000 cores 1000 routers plus 12 SRAM blocks) that run independently of each other, can change their frequencies and stop in a very short time and start up again in order to save energy.

Also to save energy, the Kilo Core waived explicit cache. There are in each core 128 × 40-bit instruction memory, 256 x 16-bit data memory, and twelve times the above-mentioned 64K SRAM.

Extra core chip having a plurality of applications in parallel The Kilo core chip processes multiple applications in parallel.(Image: University of California, Davis)

Different core groups of the Kilo Core can perform independently of each other computing tasks simultaneously; in their paper the researchers, for example, wireless calculations, FFT and AES mention parallel.

Work on the kilos core chip the University of California was funded by the US Department of Defense. Already in 2006, which later acquired company report had proposed a kilo core chip, which had demonstrated a 256-core chip, among others, for the processing of video data.(Ciw)